Interconnect lines in IC's are typically composed of metal segments. In most IC's, interconnect lines are disposed in vertical layers wherein the interconnect lines in adjacent layers are orthogonal to each other. A metallization line formed on one layer can be connected to a metallization line formed on another layer by a via. During operation of IC's, electric fields are induced between metallization lines positioned horizontally adjacent to each other in the same layer and between metallization lines positioned vertically overlapping to each other in overlapping layers.
Capacitance of an interconnect line in an IC can cause propagation delays for signals propagating through the interconnect line. Signal propagation delays slow down the speed of an IC. Therefore, it is important for IC designers to determine the capacitance associated with interconnect lines in IC's in order to assess the speed at which a new design or layout might run. Propagation delays through interconnect lines may increase as interconnect line lengths increase or interconnect line packing density increases. In very large scale integration (VLSI) IC's, which include interconnect lines with very small spacings and very large heighth-to-width ratios, the capacitance of the interconnect lines is a limiting factor in the functioning speed of the IC. Without a reliable method for determining the capacitance of interconnect lines in an IC, an IC designer cannot predict how the interconnect line will function prior to design, fabrication, and test.
Various prior art numerical analysis methods for estimating capacitances of interconnect lines in IC's are well known. However, these numerical analysis methods are very rigorous and time consuming and therefore not amenable to use in computer aided design systems (CAD systems). CAD systems utilize various empirical methods for estimating capacitance of interconnect lines. Prior art empirical methods are less rigorous and less time consuming, but also less accurate than the numerical analysis methods. In typical prior art empirical methods, metallization lines, disposed in layers adjacent to an interconnect line under test, are modeled as ground planes. Sakurai provides one example of an empirical method for estimating capacitance per unit length of an interconnect line in the presence of a single ground plane. "Simple Formula for Two- and Three-Dimensional Capacitances", by T. Sakurai and K. Tamaru, Transactions on Electron devices, Vol. ED-30, No. 2, February 1983, pages 183-185. However, in order to determine the capacitance of an interconnect line in an integrated circuit, it is necessary to consider capacitive coupling of the interconnect line with two ground planes present. This is due to the fact that metallization lines, approximated as ground planes, are often positioned in adjacent vertical layers above and below the interconnect line under test in an integrated circuit.
One prior art CAD system, the "Compass Interconnect Extract Tool", employs an empirical method for estimating the capacitance of a single interconnect line positioned between two ground planes. However, the prior art Compass method and apparatus yields inaccurate estimates of the capacitance of an interconnect line in the presence of two ground planes. One problem contributing to a lack of accuracy of the prior art method is an over counting of fringing capacitance due to fringe electric fields induced between sidewalls of the interconnect line under test and ground planes. In the case of an interconnect line positioned between a top ground plane and a bottom ground plane, fringe electric fields are induced between the interconnect line and the top and bottom ground planes. A top fringe electric field is induced between the interconnect line and the top ground plane. A bottom fringe electric field is induced between the interconnect line and the bottom ground plane. The Compass method and other prior art methods do not take into account perturbative effects caused by the simultaneous presence of the two ground planes on the respective fringe electric fields and thus their effects on the capacitance.
Thus, a need exists for a fast and accurate empirical method for estimating the capacitance of an interconnect line in the presence of two ground planes. More specifically, a need exists for such an empirical method in which perturbative effects, of the top and bottom ground planes on the fringe electric fields and capacitance, are taken into account. A further need exists for such an empirical method which is fast, does not require excessive processing time, and also produces extremely accurate results.